**HW #1 Part-2 & Part-3 **

Due: Beofre 1/18 class time. No submission and Part-2 and Part-3 won’t be graded

part-1: Fill out the student information link: please see Canvas.

In this assignment, you will get ready to do project #1 and HW #2. Please see Useful Links for the links.

Part 2 Install verilator/GTK Wave and test it. Please look at MAC Linux Windows to install verilator/GTK Wave and test the installation.

Part 3 Pipeline design

Using RISC-V tiny ISA, design a 5-stage pipeline. The ISA manuals can be found Useful Links In project #1, you will write a 5-stage pipeline design using verilog. Please consider how to handle branch stalls and data hazard stalls.