GT CS 3220 Processor Design
Where to submit: Canvas
(3 points)
Due: Jan 25 (W) This is an individual assignment.
In this assignment, you will implement a synchronous FIFO in Verilog.
$ git clone https://github.com/gt-cs3220/gt-cs3220.github.io.git
$ cd gt-cs3220.github.io/Spring_2023/
A FIFO is a structure that stores data and handles the input-output in first-in first-out fashion. Important points to note:
Parameters:
Input signals:
Output signals:
Critical functionality:
HINT: Use pointers to track the head and tail of the FIFO.
We have provided the skeleton code for the module (fifo.v).
NOTE: DO NOT CHANGE THE PORT OR MODULE DEFINITIONS. Implement functionality for the main buffer structure in the FIFO and functionality for handling all status signals.
We have provided the testbench code (fifo.cpp).
e.g.) verilator -Wall –trace –exe –build -cc fifo.v fifo.cpp
OR
What to submit:
How to test the correctness: Testbench runs on the verilog module without errors.
Grading Policy:
(3 points) If you pass the provided test code.
Partial grading Policy: Partial grade points are very limited.
FAQ [Q] When I compile the files, it generates errors. What should I do? [A] You need to complete the code. The provided code is incomplete, so it will generate errors
[Q] Can I modify fifo.cpp file? [A] Yes, you can modify it to add more prints or other test cases
[Q] How can I debug the internal wires? [A] Please look at the trace to see all wire values in the module.
[Q] Do I need to test other test cases? [A] We will use the same test case as the provided code.